1. Field of the Prior Art
This invention relates to a general-purpose microprocessor, and particularly to a microprocessor containing a cache memory.
2. Description of the Prior Art
FIG. 1 is a structural diagram of a conventional microprocessor or CPU (Central Processing Unit). A conventional CPU 10 is mainly composed of an arithmetic processing unit 20 (PU), a memory management unit 13 (MMU), an instruction cache memory 12, a data cache memory 11 and an external bus interface unit or external bus control unit 14 (BIU). The PU 20 and the MMU 13 are connected to each other through a logic bus or instruction logic bus 15 and a data logic address bus 16. Moreover, the MMU 13 and the BIU 14 are connected to each other through physical address bus 18. Furthermore, the PU 20 and the BIU 14 are connected to each other through an internal data bus 17.
Hereinafter, operation of the conventional CPU 10 laving the composition as mentioned above will be explained. For example, when the PU 20 reads operand data, a logic address is outputted to the data logic address bus 16. Then, the data cache 11 checks whether the address is stored in the data cache 11, or the address coincides with an address value in the data cache 11. When the coincidence is recognized, since objective operand data are cached in the data cache 11, the data cache 11 transfers the data to the PU 20 through the internal data bus 17.
If there is no coincidence, since the operand data are not cached in the data cache 11, the data is transferred to the data cache 31 and the PU 20 from an external memory (not shown). Namely, the MMU 13 translates the logic address on the bus 16 into a specific physical address in the memory, and transfers the result to the BIU 14 through the physical address bus 18. Then, the BIU outputs an address corresponding to the objective data to an external address bus 30. As the result, data stored in an external memory (not shown) are transferred to the PU 20 through an external data bus 31 and the internal data bus 17. At the same time, the data are written in the data cache 11. In this manner, the reading operation for operand data is completed.
While the PU 20 and the BIU 14 use the internal data bus 17 in common, the BIU 14 cannot use the internal data bus 17, for example, while data are being transferred from an external memory to the CPU 20 through the internal data bus 17. Accordingly, the BIU 14 cannot transfer data to the data cache memory 11 or the instruction cache memory 12 through the internal data bus 17 when the PU 20 is using the internal data bus 17.
When the BIU 14 renews the data cache 11 or the instruction cache 12 through the internal data bus 17, the PU 20 can not use the internal data bus 17. Particularly, when the line size of these caches 11 and 12 is relatively large, the BIU 14 occupies the internal data bus 17 for a long time. During this time, the PU 20 must be in the time-waiting state, thus the throughput of the CPU 10 as a whole is reduced.
The mentioned problems are in the case of the reading operation of operands data. Moreover, in other operation, for example an instruction fetch operation, similar problems are also caused because the internal data bus 17 is used in common by the PU 20 and the BIU 14.
Furthermore, in the structure of the conventional microprocessor, when the number of cache memories or the like is increased, it is necessary to increase the number of memory management units (MMU) 13 and the capacity of the internal data bus 17 for controlling operation of these cache memories. Accordingly, the structure of the microprocessor must become more complicated. Moreover, there are similar problems in the case of a multiprocessor comprising a plurality of processors.